gate level simulation
英 [ɡeɪt ˈlevl ˌsɪmjuˈleɪʃn]
美 [ɡeɪt ˈlevl ˌsɪmjuˈleɪʃn]
网络 门级仿真; 仿真; 逻辑闸层次模拟
双语例句
- The LOP circuit module is described in gate level with VHDL, which has passed the logic simulation and verification. It is applied to the design of floating-point adder.
LOP电路设计采用VHDL语言门级描述，已通过逻辑仿真验证，并在浮点加法器的设计中得到应用。 - Gate-level simulation shows that it is right and rational.
并通过RTL级仿真、综合布线后的门级仿真、表明了设计的合理性和止确性。 - This macromodel only consumes 1%~ 0.1% run time of the gate level simulation and its relative error is no more than 20%.
与门级模拟结果相比较，本模型的计算时间下降了2～3个数量级，而相对误差不超过20%。 - Gate-level simulation shows that it is right and rational. The netlist of synthesis has passed the gate-level simulation.
最后，对逻辑综合产生的门级网表进行了门级仿真。